\doxysection{CRS\+\_\+\+Type\+Def Struct Reference}
\hypertarget{struct_c_r_s___type_def}{}\label{struct_c_r_s___type_def}\index{CRS\_TypeDef@{CRS\_TypeDef}}


Clock Recovery System.  




{\ttfamily \#include $<$stm32h723xx.\+h$>$}

\doxysubsubsection*{Public Attributes}
\begin{DoxyCompactItemize}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_c_r_s___type_def_a8f1000451ee16f2da1ba6cc3411dd36a}{CR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_c_r_s___type_def_ad51dab454cab135414e565504d776a30}{CFGR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_c_r_s___type_def_a20a87b708e338746006cdaa103116293}{ISR}}
\item 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t \mbox{\hyperlink{struct_c_r_s___type_def_a7caf1bbdc605d9bbd79577470c2f531b}{ICR}}
\end{DoxyCompactItemize}


\doxysubsection{Detailed Description}
Clock Recovery System. 

\label{doc-variable-members}
\Hypertarget{struct_c_r_s___type_def_doc-variable-members}
\doxysubsection{Member Data Documentation}
\Hypertarget{struct_c_r_s___type_def_ad51dab454cab135414e565504d776a30}\index{CRS\_TypeDef@{CRS\_TypeDef}!CFGR@{CFGR}}
\index{CFGR@{CFGR}!CRS\_TypeDef@{CRS\_TypeDef}}
\doxysubsubsection{\texorpdfstring{CFGR}{CFGR}}
{\footnotesize\ttfamily \label{struct_c_r_s___type_def_ad51dab454cab135414e565504d776a30} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t CRS\+\_\+\+Type\+Def\+::\+CFGR}

CRS configuration register, Address offset\+: 0x04 \Hypertarget{struct_c_r_s___type_def_a8f1000451ee16f2da1ba6cc3411dd36a}\index{CRS\_TypeDef@{CRS\_TypeDef}!CR@{CR}}
\index{CR@{CR}!CRS\_TypeDef@{CRS\_TypeDef}}
\doxysubsubsection{\texorpdfstring{CR}{CR}}
{\footnotesize\ttfamily \label{struct_c_r_s___type_def_a8f1000451ee16f2da1ba6cc3411dd36a} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t CRS\+\_\+\+Type\+Def\+::\+CR}

CRS ccontrol register, Address offset\+: 0x00 \Hypertarget{struct_c_r_s___type_def_a7caf1bbdc605d9bbd79577470c2f531b}\index{CRS\_TypeDef@{CRS\_TypeDef}!ICR@{ICR}}
\index{ICR@{ICR}!CRS\_TypeDef@{CRS\_TypeDef}}
\doxysubsubsection{\texorpdfstring{ICR}{ICR}}
{\footnotesize\ttfamily \label{struct_c_r_s___type_def_a7caf1bbdc605d9bbd79577470c2f531b} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t CRS\+\_\+\+Type\+Def\+::\+ICR}

CRS interrupt flag clear register, Address offset\+: 0x0C \Hypertarget{struct_c_r_s___type_def_a20a87b708e338746006cdaa103116293}\index{CRS\_TypeDef@{CRS\_TypeDef}!ISR@{ISR}}
\index{ISR@{ISR}!CRS\_TypeDef@{CRS\_TypeDef}}
\doxysubsubsection{\texorpdfstring{ISR}{ISR}}
{\footnotesize\ttfamily \label{struct_c_r_s___type_def_a20a87b708e338746006cdaa103116293} 
\mbox{\hyperlink{core__armv81mml_8h_aec43007d9998a0a0e01faede4133d6be}{\+\_\+\+\_\+\+IO}} uint32\+\_\+t CRS\+\_\+\+Type\+Def\+::\+ISR}

CRS interrupt and status register, Address offset\+: 0x08 

The documentation for this struct was generated from the following file\+:\begin{DoxyCompactItemize}
\item 
C\+:/\+Users/\+ASUS/\+Desktop/dm-\/ctrl\+H7-\/balance-\/9025test/\+Drivers/\+CMSIS/\+Device/\+ST/\+STM32\+H7xx/\+Include/\mbox{\hyperlink{stm32h723xx_8h}{stm32h723xx.\+h}}\end{DoxyCompactItemize}
